Deep aspect ratio silicon etching is one of the principal technologies currently being used to fabricate microstructure devices, and is an enabling technology for many microelectromechanical systems (MEMS) applications. A conventionally used single-crystal silicon deep aspect ratio etch process is based upon a cyclic plasma etch/polymer deposition method, also known as Rapid Alternating Parameters (RAP) process, or a Bosch process.
FIGS. 1A-F illustrate a conventional method of etching silicon in a Bosch process.
FIG. 1A illustrates a first step in the conventional Bosch etching process.
As shown in the figure, a silicon layer 100 has a top surface 102, upon which a photoresist mask 104 is disposed. Photoresist mask 104 includes a window 106, wherein a portion of surface 102 is exposed.
Silicon layer 100 with photoresist mask 104 is placed in a standard silicon etching chamber to begin the etching process.
FIG. 1B illustrates a second step in the conventional Bosch etching process.
As shown in the figure, the portion of silicon layer 100 that is exposed through window 106 has been etched so as to create via 108. Via 108 includes a side wall 110 and a bottom surface 112.
Via 108 is created by generating an etching gas plasma in the etching chamber. An example gas used to etch silicon is SF6, however other gases may be used. The etch depth is controlled by introducing the gas into the chamber at a specific flow rate and pressure for a certain amount of time, with silicon layer 100 at a specific voltage, or bias, and RF power is provided to form an etch plasma. The gas removes the silicon in an isotropic manner. Isotropy is uniformity in all directions. As such, the etching process removes silicon in all directions equally. In three-dimensional space, the result of the isotropic removal is a spherical hole. This is indicated in the figure by the circular shape of side wall 110 and bottom surface 112 of via 108 in two-dimensional space.
FIG. 1C illustrates a third step in the conventional Bosch etching process.
As shown in the figure, protective layer 116 is disposed upon both a top surface 114 of photoresist mask 104, side wall 110 and bottom surface 112 of via 108.
Protective layer 116 may include a polymer that decreases lateral etching as compared to vertical etching. Accordingly, the width of via 108 docs not increase throughout the process. While other materials may be used, one non-limiting example of a material used for a protective layer is C4F8.
FIG. 1D illustrates a fourth step in the conventional Bosch etching process.
As shown in the figure, most of protective layer 116 has been removed to leave protective surface 118 disposed on side wall 110 of via 108. Protective surface 118 docs not cover bottom surface 112. As such, bottom surface 112 is exposed through a window 120 of protective surface 118.
In order to continue vertical etching into silicon layer 100, without lateral etching, it is necessary to clear protective layer 116 from bottom surface 112, while maintaining protective surface 118 on side wall 110. Without protective surface 118, additional etching steps would increase the width of via 108 due to the isotropic nature of the etching process. Protective layer 116 may be removed from bottom surface 112 using known methods as part of a conventional Bosch process.
FIG. 1E illustrates a fifth step in the conventional Bosch etching process. As shown in the figure, silicon layer 100 has been etched a second time to create via 126, with side walls 110 and 122 and bottom surface 124.
Due to the isotropic nature of the etching process, the second etch process removes protective layer 118 and also creates via 126. Creating via 126 does not increase the size of side wall 110 as the etching gas does not contact side wall 110 due to protective layer 118.
FIG. 1F illustrates a final via produced by multiple cycles in the conventional Bosch etching process.
As shown in the figure, silicon layer 100 has been etched a plurality of times to create via 128. The process of etching and deposition continues in an alternating fashion until a via of the desired depth is created.
The isotropic nature of the etching process tends to create vias that are essentially semi-spherical because the etching gas has no directional component and attacks all surfaces equally. The result is that each etch undercuts the previous etch such that the wall of the completed via has an undulating nature with peaks and troughs. The collection of peaks and troughs are called scallops. Depending on the processing parameters, the depth and width of the scallops can change. This will be described in greater detail with reference to FIGS. 2-3.
FIG. 2 illustrates an enlarged view of side wall 110 and 122 of FIG. 1E.
As shown in FIG. 2, side walls 110 and 122 form a scallop 202, which includes peaks 204 and 206. Scallop 202 has a width, W, measured as the longest horizontal distance between peak 204 or 206 and side wall 110. Scallop 202 also has a depth, H, measured as the vertical distance between peaks 204 and 206. Width, W, and depth, H, are variables that are controlled by the processing parameters under which the via is created. For example, one process incorporating certain parameters for a given amount of time will create scallops of a specific size. Increased exposure time, while maintaining all other parameters constant, would result in a large scallop.
If a less aggressive etching process is performed, the relative difference between the peaks and troughs of the scallops may be decreased. However, many more scallops will be formed to reach the same depth. An additional scallop is formed each time the etching process is repeated. This will be described with reference to FIG. 3.
FIG. 3 illustrates another example of side walls created by etching a via with a conventional Bosch process using different etching parameters.
As shown in the figure, a side wall 302 includes a plurality of peaks, a sample indicated by peaks 306 and 308. A scallop 310 has a width, w, measured as the longest horizontal distance between peak 306 or 308 and side wall 302. Scallop 310 also has a depth, h, measured as the vertical distance between peaks 306 and 308.
When performing a more aggressive etching process, a via of the desired depth can be created relatively quickly with a single etching step. A disadvantage of performing this aggressive etch is that, due to the isotropic nature of the etching process, the scallop created during this process would be very large.
In contrast, when performing a less aggressive etching process, creating a via of the desired depth will take more time. The increase in total processing time is a result of performing multiple etching steps for a short amount of time. The advantage of performing a less aggressive etch is that each scallop created is much smaller, however many more scallops are required to produce a via of the same depth.
For optimum semiconductor performance, the plurality of scallops created during the etching process would be completely removed, leaving a smooth-walled via. There are methods to reduce the profile of the scallops by modifying processing parameters, however there is no known method to completely eliminate scallops from the side wall of a via.
U.S. Pat. No. 6,846,746 (Ratner et al.) provides a method to reduce scallops, but not fully eliminate them, in etch applications. Scallop reduction is accomplished by oxidation of the scallop peaks, followed by an etch suitable for removal of silicon oxides. The primary gases disclosed are CF4 and O2, though the patent also describes a non-oxidative process with SF6, and there is a brief mention of NF3. The parameters disclosed for processing with SF6 and NF3 differ greatly. The disclosed flow range for fluorine-containing gases: is 2-50 sccm in combination with a flow of He of 2-200 sccm, at a pressure of 1-30 mtorr. Further, the process described in Ratner et al. uses a bias of 10-40V in the processing chamber. This bias directs fluorine ions to chemically react with the scalloped side walls. The chemical reaction takes a large amount of time and creates unwanted undercutting within the trench.
Published US Patent application 2009/0272717 A1 (Pamarthy et al.) also provides a method to reduce scallops, but not fully eliminate them, in etch applications. Scallop reduction is accomplished by invoking fast gas switching in an attempt to overcome the formation of scallops, however the disclosed on/off times are greater than 1 second. Additionally, the unused gas is dumped into an exhaust stream, thereby wasting about half the gas, which is undesirable. Furthermore, the proposed method results in typical scallop measurements of 1.5 microns.
The scallops discussed above are undesirable, and no conventional etching process completely eliminates scallops.
What is needed is an improved etching process that does not produce a scalloped via. This processing method must maintain the integrity of the via, meaning the via dimensions must not be increased.